Parallel Computer Architecture and Instruction-Level Parallelism

Topic 08


Instruction-Level Parallelism and parallel processing techniques are present in most contemporary computing systems. The scope of this topic includes (but is not limited to) parallel computer architectures, processor architecture (architecture and microarchitecture as well as compilation), the impact of emerging microprocessor architectures on parallel computer architectures, innovative memory designs to hide and reduce the access latency, multi-threading, and the impact of emerging applications on parallel computer architecture design.

Our aim is to bring together researchers in the fields of parallel computer architecture and processor architecture. We invite researchers with interest in both conventional and non-conventional approaches to participate. Papers are being sought on all aspects of parallel computer architecture, processor architecture and microarchitecture, including (but not limited to) the following list of topics.


  • parallel computer architecture
  • ILP architectures and designs
  • microarchitecture and implementation techniques
  • performance evaluation and benchmarking of processor architectures
  • multithreaded processors
  • single chip multiprocessors
  • memory system designs
  • multiprocessor and vector architectures
  • theoretical foundations of processor architectures
  • compilation techniques for parallel computer architectures
  • application-specific and embedded processors
  • stream processing microarchitectures
  • signal processors
  • network processors
  • reconfigurable processors
  • asynchronous processors

Global Chair

Prof. Stamatis Vassiliadis

Computer Engineering Laboratory

Delft University of Technology, The Netherlands


Vice Chairs

Prof. Nikitas J. Dimopoulos

Electrical & Computer Engineering

University of Victoria, Canada

Email: nikitas@ECE.UVic.CA  

Dr. Jean-François Collard

HP Labs 3U

Hewlett-Packard Company


Local Chair

Prof. Arndt Bode

Lehrstuhl für Rechnertechnik und Rechnerorganisation

Institut für Informatik

Technische Universität München