Topic 08
Parallel Computer Architecture and Instruction-Level Parallelism

Topic Description and Chairs
Session 08.1: Caches
Session 08.2: Instruction and Thread Level Parallelism
Session 08.3: Industrial System Software

Session 08.1: Caches

Time Wednesday, August 27, 2003, 14.00 - 15.30
Location HS 3
Chair Arndt Bode
   
14.00 - 14.30 Cache Performance Optimizations for Parallel Lattice Boltzmann Codes
    J. Wilke, Th. Pohl, M. Kowarschik, and U. Rüde
14.30 - 15.00 Counteracting Bank Misprediction in Sliced First-Level Caches
    E.F. Torres, P. Ibañez, V. Viñals, and J. M. Llaberia
15.00 - 15.15 Compression in Data Caches with Compressible Field Isolation for Recursive Data Structures (Research Note)
    Masamichi Takagi and Kei Hiraki
15.15 - 15.30 Value Compression to Reduce Power in Data Caches (Research Note)
    C. Aliagas, C. Molina, M. Garcia, A. Gonzalez, and J. Tubella

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Session 08.2: Instruction and Thread Level Parallelism

Time Wednesday, August 27, 2003, 16.00 - 17.45
Location HS 3
Chair Nikitas Dimopoulos
   
16.00 - 16.30 Trace Substitution
    H.Vandierendonck, H. Logie, and K. De Bosschere
16.30 - 17.00 Optimizing a Decoupled Front-End Architecture: the Indexed Fetch Target Buffer (iFTB)
    J. C. Moure, D. I. Rexachs, and E. Luque
17.00 - 17.30 Clustered Microarchitecture Simultaneous Multithreading
    Seong-Won Lee and J.-L. Gaudiot
17.30 - 17.45 Compiler-Assisted Thread Level Control Speculation (Research Note)
    Hideyuki Miura, Luong Dinh Hung, Chitaka Iwama, Daisuke Tashiro, Niko Demus Barli, Shuichi Sakai, and Hidehiko Tanaka

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Session 08.3: Industrial System Software

Time Wednesday, August 27, 2003, 18.00 - 19.00
Location HS 3
Chair Emilio Luque
   
18.00 - 18.30 An Overview of the Blue Gene/L System Software Organization (Distinguished Paper)
    G. Almási, R. Bellofatto, J. Brunheroto, C. CaŘscaval, J. G. Castaños, L. Ceze, P. Crumley, C. Ch. Erway, J. Gagliano, D. Lieber, X. Martorell, J. E. Moreira, A. Sanomiya, and K. Strauss
18.30 - 18.45 An Enhanced Trace Scheduler for SPARC Processors (Research Note)
    S. Kalogeropulos

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